A design may be described by using a hardware description language (“HDL”), such as Verilog or VHDL for example. However, using an HDL is more for circuit design, and many software engineers are not familiar with these types of languages and/or circuit design. Furthermore, as technology advances, applications and designs may be architected on a higher functional level than at the HDL level, such as using objects and classes for example. Along those lines, a high-level synthesis (“HLS”) tool that uses a programming language, such as ANSI C, C++ and/or SystemC for example, may be used. An HLS tool may be used to translate an application or design specified in a programming language into an HDL circuit design.
An application or a design (“design”) in a programming language may be synthesized by an HLS tool, and such synthesis may be used in order to better understand behavior of such design prior to manufacture. Latency is a significant Quality of Result (“QoR”) metric used to evaluate quality of a design prior to manufacture.
Along those lines, an HLS tool that could be used to provide accurate latency estimation would be useful.